The subject matter disclosed herein relates to semiconductors and, more specifically, to silicon carbide (SiC) devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Typically, silicon carbide (SiC) based devices (e.g., transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) insulated gate bipolar transistors (IGBTs) or the like) are operated with higher gate-source drive voltage as compared to silicon (Si) based devices. In addition, such devices typically employ short channels, tight cell pitch and include heavily doped (e.g., a sheet doping density (concentration) greater than about 2.5×1014 cm−2, or in some embodiments, for example where a box profile depth is about 0.25 um, a doping concentration greater than about 1×1019 cm−3) source regions to obtain a low on-state resistance (on-resistance), Rds(on). As a result, in these use conditions SiC based devices often exhibit up to approximately twenty times nominal current density before saturation occurs, often exhibiting a much softer “quasi” saturation of drain family I-V characteristics. However, such features may have a detrimental impact on the ability of the device to withstand short-circuit faults in certain applications, for example, such as power conversion systems. In addition, a strong negative temperature dependence of threshold voltage typically exhibited in SiC MOS based devices can result in an instantaneous increase of saturation current during fault conditions as local heat increases proximate one or more structures (e.g., MOS channels) occurs. Further, much of the evolution of device designs has been focused on reducing device on-state resistance, which further increases peak current under fault conditions. It is now recognized that there is a need for an improved SiC device and method of fabricating thereof.